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1. general description the lpc12d27 are arm cortex-m0 based microcontrollers for embedded applications featuring a high level of integration and lo w power consumption. the arm cortex-m0 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration. the lpc12d27 is a dual-chip module consisting of a lpc1227 single-chip microcontroller combined with a pcf8576d universal lcd driv er in a low-cost 100-pin package. the lcd driver provides 40 segments and supports from one to four backplanes. display overhead is minimized by an on-chip di splay ram with auto-increment addressing. the lpc12d27 operate at cpu frequencies of up to 45 mhz and include 128 kb of flash memory and 8 kb of data memory. the peripheral complement of the lpc1227 microcontroller includes a micro dma controller, one fast-mode plus i 2 c interface, one ssp interface, two uart s, four general purpose timers, a 10-bit adc, two comparator s, and up to 40 general purpose i/o pins. remark: for a functional description of the lpc1227 microcontroller see the lpc122x data sheet . for a detailed description of the lcd driver see the pcf8576d data sheet . both data sheets are available at http://www.nxp.com/microcontrollers 2. features and benefits ? lcd driver ? 40 segments. ? one to four backplanes. ? on-chip display ram with auto-increment addressing. ? processor core ? arm cortex-m0 processor, running at frequencies of up to 45 mhz (one wait state from flash) or 30 mhz (zero wait states from flash). the lpc12d27 have a high score of over 45 in coremark cpu perfor mance benchmark testing, equivalent to 1.51/mhz. ? arm cortex-m0 built-in nested vectored interrupt controller (nvic). ? serial wire debug (swd). ? system tick timer. ? memory ? 8 kb sram. ? 128 kb on-chip flash programming memory. lpc12d27 32-bit arm cortex-m0 microcontroller; 128 kb flash and 8 kb sram; 40 segment x 4 lcd driver rev. 1 ? 20 september 2011 product data sheet
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 2 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller ? in-system programming (isp) and in-application programming (iap) via on-chip bootloader software. ? includes rom-based 32-bit integer division routines. ? clock generation unit ? crystal oscillator with an operating range of 1 mhz to 25 mhz. ? 12 mhz internal rc (irc) osc illator trimmed to 1 % accura cy that can optionally be used as a system clock. ? pll allows cpu operation up to the maximum cpu rate without the need for a high-frequency crystal. may be run from th e system oscillator or the internal rc oscillator. ? clock output function with divider that ca n reflect the system oscillator clock, irc clock, main clock, and watchdog clock. ? real-time clock (rtc). ? digital peripherals ? micro dma controller with 21 channels. ? crc engine. ? two uarts with fractional baud rate generation and internal fifo. one uart with rs-485 and modem support and one standard uart with irda. ? ssp/spi controller with fifo and multi-prot ocol capabilities. ? i 2 c-bus interface supporting full i 2 c-bus specification and fast-mode plus with a data rate of 1 mbit/s wit h multiple address recognition and monitor mode. i 2 c-bus pins have programmable glitch filter. ? up to 40 general purpose i/o (gpio) pins with programmable pull-up resistor, open-drain mode, programmable digital input glitch filter, and programmable input inverter. ? programmable output drive on all gpio pins. four pins support high-current output drivers. ? all gpio pins can be used as edge and level sensitive interrupt sources. ? four general purpose counter/timers with four capture inputs and four match outputs (32-bit timers) or two capture input s and two match outputs (16-bit timers). ? windowed watchdog timer (wwdt), iec-60335 class b certified. ? analog peripherals ? one 8-channel, 10-bit adc. ? two highly flexible analog comparators. comparator outputs can be programmed to trigger a timer match signal or ca n be used to emulate 555 timer behavior. ? power ? three reduced power modes: sleep, deep-sleep, and deep power-down. ? processor wake-up from deep-sleep mode via start logic using 12 port pins. ? processor wake-up from deep-power down and deep-sleep modes via the rtc. ? brownout detect with three separate thresholds each for interrupt and forced reset. ? power-on reset (por). ? integrated pmu (power management unit). ? unique device serial number for identification. ? 3.3 v power supply. ? available as 100-pin lqfp package.
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 3 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 3. applications ? white goods ? portable medical devices ? lighting control ? thermostats ? alarm systems 4. ordering information 4.1 ordering options table 1. ordering information type number package name description version LPC12D27FBD100/301 lqfp100 plastic low profile quad flat package; 100 leads; body 14 ? 14 ? 1.4 mm sot407-1 table 2. ordering options for lpc12d27 type number flash total sram uart rs-485 i 2 c/ fm+ ssp adc channels package LPC12D27FBD100/301 128 kb 8 kb 1 1 1 8 lqfp100
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 4 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 5. block diagram fig 1. lpc12d27 block diagram scl, sda lcd_scl, lcd_sda v lcd lpc1227 mcu pcf8576d lcd controller pio0, pio1, pio2 s[39:0] bp[3:0] 002aaf672
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 5 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller fig 2. lpc12d27 block diagram (microcontroller) arm cortex-m0 test/debug interface micro dma controller system bus clock generation, power control, system functions xtalin xtalout reset clocks and controls swd crc engine lpc1227 master 128 kb flash slave 8 kb sram slave rom slave slave 002aag501 gpio ports windowed wdt ioconfig real-time clock system control clkout ssp/spi uart0 rs-485 i 2 c-bus 32-bit counter/timer 0/1 sck ssel miso mosi 4 x mat 4 x cap sda scl uart1 txd1 rxd1 16-bit counter/timer 0/1 2 x mat 2 x cap rxd0 txd0 dtr0, dsr0, cts0, dcd0, ri0, rts0 10-bit adc micro dma registers comparator0/1 ad[7:0] acmp0/1_i[3:0] acmp0/1_o vref_cmp ahb-lite bus ahb-abb bridge high-speed gpio rtcxout rtcxin
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 6 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller fig 3. lcd display controller block diagram 40 002aaf673 lcd bias generator lcd voltage selector pcf8576d backplane outputs display controller command decoder write data control display ram 40 x 4-bit output bank select and blink control display register display segment outputs data pointer and auto increment subaddress counter clock select and timing oscillator input filters blinker timebase power-on reset i 2 c-bus controller bp0 bp2 bp1 bp3 v dd osc sync s0 to s39 lcd_sda lcd_scl clk v ss(lcd) v lcd
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 7 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 6. pinning information 6.1 pinning fig 4. pin configuration lqfp100 package lpc12d27 swdio/pio0_25 s29 swclk/pio0_26 s28 pio0_27 s27 pio0_28 s26 pio0_29 s25 pio0_0 s24 pio0_1 s23 pio0_2 s22 pio0_3 s21 pio0_4 s20 pio0_5 s19 pio0_6 s18 pio0_7 s17 pio0_8 s16 reset/pio0_13 s10 pio0_14 s9 pio0_15 s8 pio0_16 s7 pio0_17 pio0_9 pio2_0 pio0_10 pio0_11 pio0_12 s6 s15 s14 s13 s12 s11 pio0_18 s5 r/pio0_30 pio0_24 r/pio0_31 pio0_23 r/pio1_0 pio0_22 s34 pio0_21 s35 pio0_20 s36 pio0_19 s37 vref_cmp s38 xtalout s39 xtalin lcd_ sda v ssio lcd_ scl v dd(io) sync rtcxin clk rtcxout v dd v dd(3v3) bp3 pio1_2 s0 r/pio1_1 s1 s33 s2 s32 s3 v ss(lcd) v lcd bp0 bp2 bp1 s31 v ss pio1_6 pio1_5 pio1_4 pio1_3 s4 s30 002aag502 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 56 55 54 53 52 51 15 16 17 18 19 61 60 59 58 57 26 27 28 29 30 31 32 33 34 35 36 37 38 39 45 46 47 48 49 50 10 0 99 98 97 96 95 94 93 92 91 90 89 88 87 81 80 79 78 77 76 40 41 42 43 44 86 85 84 83 82
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 8 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 6.2 pin description all pins except the supply pins and the lcd pins can have more than one function as shown in ta b l e 3 . the pin function is selected throug h the pin?s iocon register in the ioconfig block. the mu ltiplexed functions include the c ounter/timer inputs and outputs, the uart receive, transmit, and control fu nctions, and the serial wire debug functions. for each pin, the default function is list ed first together with the pin?s reset state. table 3. lpc12d27 lqfp100 pin description symbol pin start logic input reset state [1] type description microcontroller pins pio0_0 to pio0_31 i/o port 0 ? port 0 is a 32-bit i/o port with individual direction and function controls for each bit. the operation of port 0 pins depends on the function selected through the ioconfig register block. pio0_0/rts0 6 [2] yes i; pu i/o pio0_0 ? general purpose digital input/ output pin. also serves as wake-up pin from deep-sleep mode. o rts0 ? request to send output for uart0. pio0_1/rxd0/ ct32b0_cap0/ ct32b0_mat0 7 [2] yes i; pu i/o pio0_1 ? general purpose digital input/ output pin. also serves as wake-up pin from deep-sleep mode. i rxd0 ? receiver input for uart0. i ct32b0_cap0 ? capture input, channel 0 for 32-bit timer 0. o ct32b0_mat0 ? match output, channel 0 for 32-bit timer 0. pio0_2/txd0/ ct32b0_cap1/ ct32b0_mat1 8 [2] yes i; pu i/o pio0_2 ? general purpose digital input/ output pin. also serves as wake-up pin from deep-sleep mode. o txd0 ? transmitter output for uart0. i ct32b0_cap1 ? capture input, channel 1 for 32-bit timer 0. o ct32b0_mat1 ? match output, channel 1 for 32-bit timer 0. pio0_3/dtr0 / ct32b0_cap2/ ct32b0_mat2 9 [2] yes i; pu i/o pio0_3 ? general purpose digital input/ output pin. also serves as wake-up pin from deep-sleep mode. o dtr0 ? data terminal ready output for uart0. i ct32b0_cap2 ? capture input, channel 2 for 32-bit timer 0. o ct32b0_mat2 ? match output, channel 2 for 32-bit timer 0. pio0_4/ ct32b0_cap3/ ct32b0_mat3 10 [2] yes i; pu i/o pio0_4 ? general purpose digital input/ output pin. also serves as wake-up pin from deep-sleep mode. i dsr0 ? data set ready input for uart0. i ct32b0_cap3 ? capture input, channel 3 for 32-bit timer 0. o ct32b0_mat3 ? match output, channel 3 for 32-bit timer 0. pio0_5/dcd0 11 [2] yes i; pu i/o pio0_5 ? general purpose digital input/ output pin. also serves as wake-up pin from deep-sleep mode. i dcd0 ? data carrier detect input for uart0.
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 9 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller pio0_6/ri0 / ct32b1_cap0/ ct32b1_mat0 12 [2] yes i; pu i/o pio0_6 ? general purpose digital input/ output pin. also serves as wake-up pin from deep-sleep mode. i ri0 ? ring indicator i nput for uart0. i ct32b1_cap0 ? capture input, channel 0 for 32-bit timer 1. o ct32b1_mat0 ? match output, channel 0 for 32-bit timer 1. pio0_7/cts0 / ct32b1_cap1/ ct32b1_mat1 13 [2] yes i; pu i/o pio0_7 ? general purpose digital input/ output pin. also serves as wake-up pin from deep-sleep mode. i cts0 ? clear to send input for uart0. i ct32b1_cap1 ? capture input, channel 1 for 32-bit timer 1. o ct32b1_mat1 ? match output, channel 1 for 32-bit timer 1. pio0_8/rxd1 /ct32b1_cap2/ ct32b1_mat2 14 [2] yes i; pu i/o pio0_8 ? general purpose digital input/ output pin. also serves as wake-up pin from deep-sleep mode. i rxd1 ? receiver input for uart1. i ct32b1_cap2 ? capture input, channel 2 for 32-bit timer 1. o ct32b1_mat2 ? match output, channel 2 for 32-bit timer 1. pio0_9/txd1/ ct32b1_cap3/ ct32b1_mat3 15 [2] yes i; pu i/o pio0_9 ? general purpose digital input/ output pin. also serves as wake-up pin from deep-sleep mode. o txd1 ? transmitter output for uart1. i ct32b1_cap3 ? capture input, channel 3 for 32-bit timer 1. o ct32b1_mat3 ? match output, channel 3 for 32-bit timer 1. pio0_10/scl 17 [3] yes i; ia i/o pio0_10 ? general purpose digital input/ output pin. also serves as wake-up pin from deep-sleep mode. i/o scl ? i 2 c-bus clock input/output. pio0_11/sda/ ct16b0_cap0/ ct16b0_mat0 18 [3] yes i; ia i/o pio0_11 ? general purpose digital input /output pin. also serves as wake-up pin from deep-sleep mode. i/o sda ? i 2 c-bus data input/output. i ct16b0_cap0 ? capture input, channel 0 for 16-bit timer 0. o ct16b0_mat0 ? match output, channel 0 for 16-bit timer 0. pio0_12/clkout/ ct16b0_cap1/ ct16b0_mat1 19 [7] no i; pu i/o pio0_12 ? general purpose digital input/output pin. a low level on this pin in during reset starts the isp command handler. high-current output driver. o clkout ? clock out pin. i ct16b0_cap1 ? capture input, channel 0 for 16-bit timer 0. o ct16b0_mat1 ? match output, channel 1 for 16-bit timer 0. reset /pio0_13 20 [4] no i; pu i reset ? external reset input: a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. i/o pio0_13 ? general purpose digital input/output pin. pio0_14/sck 21 [2] no i; pu i/o pio0_14 ? general purpose digital input/output pin. i/o sck ? serial clock for ssp. table 3. lpc12d27 lqfp100 pin description ?continued symbol pin start logic input reset state [1] type description
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 10 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller pio0_15/ssel/ ct16b1_cap0/ ct16b1_mat0 22 [2] no i; pu i/o pio0_15 ? general purpose digital input/output pin. i/o ssel ? slave select for ssp. i ct16b1_cap0 ? capture input, channel 0 for 16-bit timer 1. o ct16b1_mat0 ? match output, channel 0 for 16-bit timer 1. pio0_16/miso/ ct16b1_cap1/ ct16b1_mat1 23 [2] no i; pu i/o pio0_16 ? general purpose digital input/output pin. i/o miso ? master in slave out for ssp. i ct16b1_cap1 ? capture input, channel 1 for 16-bit timer 1. o ct16b1_mat1 ? match output, channel 1 for 16-bit timer 1. pio0_17/mosi 24 [2] no i; pu i/o pio0_17 ? general purpose digital input/output pin. i/o mosi ? master out slave in for ssp. pio0_18/swclk/ ct32b0_cap0/ ct32b0_mat0 25 [2] no i; pu i/o pio0_18 ? general purpose digital input/output pin. i swclk ? serial wire clock, alternate location. i ct32b0_cap0 ? capture input, channel 0 for 32-bit timer 0. o ct32b0_mat0 ? match output, channel 0 for 32-bit timer 0. pio0_19/acmp0_i0/ ct32b0_cap1/ ct32b0_mat1 95 [5] no i; pu i/o pio0_19 ? general purpose digital input/output pin. i acmp0_i0 ? input 0 for comparator 0. i ct32b0_cap1 ? capture input, channel 1 for 32-bit timer 0. o ct32b0_mat1 ? match output, channel 1 for 32-bit timer 0 pio0_20/acmp0_i1/ ct32b0_cap2/ ct32b0_mat2 96 [5] no i; pu i/o pio0_20 ? general purpose digital input/output pin. i acmp0_i1 ? input 1 for comparator 0. i ct32b0_cap2 ? capture input, channel 2 for 32-bit timer 0. o ct32b0_mat2 ? match output, channel 2 for 32-bit timer 0. pio0_21/acmp0_i2/ ct32b0_cap3/ ct32b0_mat3 97 [5] no i; pu i/o pio0_21 ? general purpose digital input/output pin. i acmp0_i2 ? input 2 for comparator 0. i ct32b0_cap3 ? capture input, channel 3 for 32-bit timer 0. o ct32b0_mat3 ? match output, channel 3 for 32-bit timer 0. pio0_22/acmp0_i3 98 [5] no i; pu i/o pio0_22 ? general purpose digital input/output pin. i acmp0_i3 ? input 3 for comparator 0. pio0_23/ acmp1_i0/ ct32b1_cap0/ ct32b1_mat0 99 [5] no i; pu i/o pio0_23 ? general purpose digital input/output pin. i acmp1_i0 ? input 0 for comparator 1. i ct32b1_cap0 ? capture input, channel 0 for 32-bit timer 1. o ct32b1_mat0 ? match output, channel 0 for 32-bit timer 1. pio0_24/acmp1_i1/ ct32b1_cap1/ ct32b1_mat1 100 [5] no i; pu i/o pio0_24 ? general purpose digital input/output pin. i acmp1_i1 ? input 1 for comparator 1. i ct32b1_cap1 ? capture input, channel 1 for 32-bit timer 1. o ct32b1_mat1 ? match output, channel 1 for 32-bit timer 1. table 3. lpc12d27 lqfp100 pin description ?continued symbol pin start logic input reset state [1] type description
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 11 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller swdio/acmp1_i2/ ct32b1_cap2/ ct32b1_mat2/pio0_25 1 [5] no i; pu i/o swdio ? serial wire debug input/output, default location. i acmp1_i2 ? input 2 for comparator 1. i ct32b1_cap2 ? capture input, channel 2 for 32-bit timer 1. o ct32b1_mat2 ? match output, channel 2 for 32-bit timer 1. i/o pio0_25 ? general purpose digital input/output pin. swclk/ acmp1_i3/ ct32b1_cap3/ ct32b1_mat3/pio0_26 2 [5] no i; pu i swclk ? serial wire clock, default location. i acmp1_i3 ? input 3 for comparator 1. i ct32b1_cap3 ? capture input, channel 3 or 32-bit timer 1. o ct32b1_mat3 ? match output, channel 3 for 32-bit timer 1. i/o pio0_26 ? general purpose digital input/output pin. pio0_27/acmp0_o 3 [7] no i; pu i/o pio0_27 ? general purpose digital input/output pin (high-current output driver). o acmp0_o ? output for comparator 0. pio0_28/acmp1_o/ ct16b0_cap0/ ct16b0_mat0 4 [7] no i; pu i/o pio0_28 ? general purpose digital input/output pin (high-current output driver). o acmpc1_o ? output for comparator 1. i ct16b0_cap0 ? capture input, channel 0 for 16-bit timer 0. o ct16b0_mat0 ? match output, channel 0 for 16-bit timer 0. pio0_29/rosc/ ct16b0_cap1/ ct16b0_mat1 5 [7] no i; pu i/o pio0_29 ? general purpose digital input/output pin (high-current output driver). i/o rosc ? relaxation oscillator for 555 timer applications. i ct16b0_cap1 ? capture input, channel 1 for 16-bit timer 0. o ct16b0_mat1 ? match output, channel 1 for 16-bit timer 0. r/pio0_30/ad0 26 [5] no i; pu i r ? reserved. configure for an alternate function in the ioconfig block. i/o pio0_30 ? general purpose digital input/output pin. i ad0 ? a/d converter, input 0. r/pio0_31/ad1 27 [5] no i; pu i r ? reserved. configure for an alternate function in the ioconfig block. i/o pio0_31 ? general purpose digital input/output pin. i ad1 ? a/d converter, input 1. pio1_0 to pio1_6 i/o port 1 ? port 1 is a 32-bit i/o port with individual direction and function controls for each bit. the operation of port 1 pins depends on the function selected through the ioconfig register block. pins pio1_7 throu gh pio1_31 are not available. r/pio1_0/ad2 28 [5] no i; pu o r ? reserved. configure for an alternate function in the ioconfig block. i/o pio1_0 ? general purpose digital input/output pin. i ad2 ? a/d converter, input 2. table 3. lpc12d27 lqfp100 pin description ?continued symbol pin start logic input reset state [1] type description
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 12 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller r/pio1_1/ad3 80 [5] no i; pu i r ? reserved. configure for an alternate function in the ioconfig block. i/o pio1_1 ? general purpose digital input/output pin. i ad3 ? a/d converter, input 3. pio1_2/swdio/ad4 81 [5] no i; pu i/o pio1_2 ? general purpose digital input/output pin. i/o swdio ? serial wire debug input/output, alternate location. i ad4 ? a/d converter, input 4. pio1_3/ad5/wakeup 82 [6] no i; pu i/o pio1_3 ? general purpose digital input/output pin. i ad5 ? a/d converter, input 5. i wakeup ? deep power-down mode wake-up pin. pio1_4/ad6 83 [5] no i; pu i/o pio1_4 ? general purpose digital input/output pin. i ad6 ? a/d converter, input 6. pio1_5/ad7/ ct16b1_cap0/ ct16b1_mat0 84 [5] no i; pu i/o pio1_5 ? general purpose digital input/output pin. i ad7 ? a/d converter, input 7. i ct16b1_cap0 ? capture input, channel 0 for 16-bit timer 1. o ct16b1_mat0 ? match output, channel 0 for 16-bit timer 1. pio1_6/ct16b1_cap1/ ct16b1_mat1 85 [2] no i; pu i/o pio1_6 ? general purpose digital input/output pin. i ct16b1_cap1 ? capture input, channel 1 for 16-bit timer 1. o ct16b1_mat1 ? match output, channel 1 for 16-bit timer 1. pio2_0 i/o port 2 ? port 2 is a 32-bit i/o port with individual direction and function controls for each bit. the operation of port 2 pins depends on the function selected through the ioconfig register block. pins pio2_1 throu gh pio2_31 are not available. pio2_0/ct16b0_cap0/ ct16b0_mat0 16 [2] no i; pu i/o pio2_0 ? general purpose digital input/output pin. i ct16b0_cap0 ? capture input, channel 0 for 16-bit timer 0. o ct16b0_mat0 ? match output, channel 0 for 16-bit timer 0. rtcxin 89 - - - input to the 32 khz oscillator circuit. rtcxout 88 - - - output from the 32 khz oscillator amplifier. xtalin 92 - - - input to the system oscillator circuit and internal clock generator circuits. xtalout 93 - - - output from the system oscillator amplifier. vref_cmp 94 - - - reference voltage for comparator. v dd(io) 90 - - - input/output supply voltage. v dd(3v3) 87 - - - 3.3 v supply voltage to the internal regulator and the adc. also used as the adc reference voltage. v ssio 91 - - - ground. v ss 86 - - - ground. lcd display pins s0 46 - v lcd [8] o lcd segment output. s1 47 - v lcd [8] o lcd segment output. table 3. lpc12d27 lqfp100 pin description ?continued symbol pin start logic input reset state [1] type description
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 13 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller s2 48 - v lcd [8] o lcd segment output. s3 49 - v lcd [8] o lcd segment output. s4 50 - v lcd [8] o lcd segment output. s5 51 - v lcd [8] o lcd segment output. s6 52 - v lcd [8] o lcd segment output. s7 53 - v lcd [8] o lcd segment output. s8 54 - v lcd [8] o lcd segment output. s9 55 - v lcd [8] o lcd segment output. s10 56 - v lcd [8] o lcd segment output. s11 57 - v lcd [8] o lcd segment output. s12 58 - v lcd [8] o lcd segment output. s13 59 - v lcd [8] o lcd segment output. s14 60 - v lcd [8] o lcd segment output. s15 61 - v lcd [8] o lcd segment output. s16 62 - v lcd [8] o lcd segment output. s17 63 - v lcd [8] o lcd segment output. s18 64 - v lcd [8] o lcd segment output. s19 65 - v lcd [8] o lcd segment output. s20 66 - v lcd [8] o lcd segment output. s21 67 - v lcd [8] o lcd segment output. s22 68 - v lcd [8] o lcd segment output. s23 69 - v lcd [8] o lcd segment output. s24 70 - v lcd [8] o lcd segment output. s25 71 - v lcd [8] o lcd segment output. s26 72 - v lcd [8] o lcd segment output. s27 73 - v lcd [8] o lcd segment output. s28 74 - v lcd [8] o lcd segment output. s29 75 - v lcd [8] o lcd segment output. s30 76 - v lcd [8] o lcd segment output. s31 77 - v lcd [8] o lcd segment output. s32 78 - v lcd [8] o lcd segment output. s33 79 - v lcd [8] o lcd segment output. s34 29 - v lcd [8] o lcd segment output. s35 30 - v lcd [8] o lcd segment output. s36 31 - v lcd [8] o lcd segment output. s37 32 - v lcd [8] o lcd segment output. s38 33 - v lcd [8] o lcd segment output. s39 34 - v lcd [8] o lcd segment output. bp0 42 - v lcd [8] o lcd backplane output. table 3. lpc12d27 lqfp100 pin description ?continued symbol pin start logic input reset state [1] type description
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 14 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller [1] pin state at reset for default function: i = input; o = output; pu = internal pull-up enabled; ia = inactive, no pull-up/dow n enabled. [2] digital i/o pin; default: pull-up enabled, no hysteresis. [3] i 2 c-bus pins; 5 v tolerant; open-drain; de fault: no pull-up/pull-down, no hysteresis. [4] digital i/o pin with reset function; default: pull-up enabled, no hysteresis. [5] digital i/o pin with analog function; default: pull-up enabled, no hysteresis. [6] digital i/o pin with analog function and wakeup function; default: pull-up enabled, no hysteresis. [7] high-drive digital i/o pin; def ault: pull-up enabled, no hysteresis. [8] see section 7.2.3 . 7. functional description 7.1 lpc1227 microcontroller see the lpc122x data sheet for a detailed functional description of the lpc1227 microcontroller. 7.2 lcd driver see the pcf8576 data sheet for a detailed functional description of the pcf8576d lcd driver. 7.2.1 general description the pcf8576d is a peripheral device which interfaces to almost any liquid crystal display (lcd) with low multiplex rates. it gene rates the drive signals for any static or multiplexed lcd containing up to four backplanes and up to 40 segments. it can be easily cascaded for larger lcd applications. the pcf8576d communicates via the two-line bidirectional i 2 c-bus. communication overheads are mi nimized by a display ram with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). please refer to pcf8576d data sheet for electrical data. bp1 44 - v lcd [8] o lcd backplane output. bp2 43 - v lcd [8] o lcd backplane output. bp3 45 - v lcd [8] o lcd backplane output. lcd_sda 35 - [8] i/o i 2 c-bus serial data input/output. lcd_scl 36 - [8] i/o i 2 c-bus serial clock input. sync 37 - [8] i/o cascade synchronization input/output. clk 38 - [8] i/o external clock input/output. v dd 39 - - - 1.8 v to 5.5 v power supply: power supply voltage for the pcf8576d. v ss(lcd) 40 - - - lcd ground. v lcd 41 - - - lcd power supply: lcd voltage. table 3. lpc12d27 lqfp100 pin description ?continued symbol pin start logic input reset state [1] type description
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 15 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 7.2.2 functional description the pcf8576d is a versatile peripheral devic e interfacing the lpc1227 microcontroller with a wide variety of lcds. it can directly dr ive any static or multiplexed lcd containing up to four backplanes and up to 40 segments. the possible display configurations of the pcf8576d depend on the number of active backplane outputs required. a selection of display configurations is shown in table 4 . the integration of the lpc1227 microcontr oller with the pcf8576d is shown in figure 1 . 7.2.3 reset state of the lcd controller and pins after power-on, the lcd controller resets to the following starting conditions: ? all backplane and segment outputs are set to v lcd . ? the selected drive mode is 1:4 multiplex with 1/3 bias. ? blinking is switched off. ? input and output bank selectors are reset. ? the i 2 c-bus interface is initialized. ? the data pointer and the subaddress counter are cleared (set to logic 0). ? the display is disabled. remark: do not transfer data on the i 2 c -bus for at least 1 ms after a power-on to allow the reset action to complete. 7.2.4 lcd bias generator fractional lcd biasing voltages are obtained from an internal voltage divider consisting of three impedances connected in series between v lcd and v ss(lcd) . the middle resistor can be bypassed to provide a 1/2 bias voltage level for the 1:2 multiplex configuration. the lcd voltage can be temperature compensated externally using the supply to pin v lcd . 7.2.5 oscillator 7.2.5.1 internal clock the internal logic of the pcf8576d and its lcd drive signals are timed either by its internal oscillator or by an external clock. the internal osc illator is enabled by connecting pin osc to pin v ss(lcd) . if the internal oscillator is used , the output from pin clk can be used as the clock signal for several pcf8576 ds in the system that are connected in cascade. table 4. selection of display configurations number of digits/characters backplanes segments 7-segment 14-segment dot matrix/elements 4 160 20 10 160 (4 ? 40) 3 120 15 7 120 (3 ? 40) 2 80 10 5 64 (2 ? 40) 14 0524 0 ( 1 ? 40)
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 16 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 7.2.6 timing the pcf8576d timing controls the internal data flow of the device. this includes the transfer of display data from the display ram to the display segment outputs. in cascaded applications, the correct timing relationship between each pcf8576d in the system is maintained by the synchron ization signal at pin sync . the timing also generates the lcd frame signal whose frequency is derived from the clock frequency. the frame signal frequency (f fr ) is a fixed division of the clock frequency (f clk ) from either the internal or an external clock: f fr = f clk /24. 7.2.7 display register a display latch holds the display data while the corresponding multiplex signals are generated. there is a one-to-one relationshi p between the data in the display latch, the lcd segment outputs, and each column of the display ram. 7.2.8 segment outputs the lcd drive section includes 40 segment outpu ts s0 to s39 which should be connected directly to the lcd. the segment output signals are generated in accordance with the multiplexed backp lane signals and with data residing in the display latch. when less than 40 segment outputs are required, the unused segment outputs should be left open-circuit. 7.2.9 backplane outputs the lcd drive section includes four backplane outputs bp0 to bp3 which must be connected directly to the lcd. the backplane output signals are generated in accordance with the selected lcd drive mode. if less than four backplane outputs are required, the unused outputs can be left open-circuit. in the 1:3 multiplex drive mode, bp3 carries the same signal as bp1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. in the 1:2 multiplex drive mode, bp0 and bp2, bp1 and bp3 all carry the same signals and may also be paired to in crease the drive capabilities. in the static drive mode the same signal is ca rried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 7.2.10 display ram the display ram is a static 40 ? 4-bit ram which stores lcd data. there is a one-to-one correspondence between the ram addresses and the segment outputs, and between the individual bits of a ram word and the backplane outputs. for details, see pcf8576d data sheet .
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 17 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 8. limiting values [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. [2] including voltage on outputs in 3-state mode. [3] the peak current is limited to 25 times the corresponding maximum current. [4] dependent on package type. [5] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. table 5. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd(3v3) supply voltage (3.3 v) 3.0 3.6 v v dd(io) input/output supply voltage 3.0 3.6 v v i input voltage on all digital pins [2] ? 0.5 +3.6 v on pins pio0_10 and pio0_11 (i 2 c-bus pins) 05.5v i dd supply current per supply pin [3] - 100 ma i ss ground current per ground pin [3] - 100 ma i latch i/o latch-up current ? (0.5v dd ) < v i < (1.5v dd ); t j < 125 ? c - 100 ma t stg storage temperature [4] ? 65 +150 ?c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1 . 5w v esd electrostatic discharge voltage human body model; all pins [5] ? 8000 +8000 v
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 18 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 9. thermal characteristics 9.1 thermal characteristics the average chip junction temperature, t j ( ? c), can be calculated using the following equation: (1) ? t amb = ambient temperature ( ? c), ? r th(j-a) = the package junction-to-ambient thermal resistance ( ? c/w) ? p d = sum of internal and i/o power dissipation the internal power dissipation is the product of i dd and v dd . the i/o power dissipation of the i/o pins is often small and many times can be negligible. however it can be significant in some applications. t j t amb p d r th j a ? ?? ? ?? += table 6. thermal characteristics v dd = 3.0 v to 3.6 v; t amb = ? ? ? symbol parameter conditions min typ max unit r th(j-a) thermal resistance from junction to ambient jedec test board; no air flow lqfp64 package -61- ? c/w lqfp48 package 86 - ? c/w r th(j-c) thermal resistance from junction to case jedec test board lqfp64 package -19- ? c/w lqfp48 package 36 - ? c/w t j(max) maximum junction temperature --150 ? c
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 19 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 10. static characteristics table 7. static characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit v dd(io) input/output supply voltage on pin v dd(io) 3.0 3.3 3.6 v v dd(3v3) supply voltage (3.3 v) 3.0 3.3 3.6 v i dd supply current active mode; v dd(3v3) =3.3v; t amb =25 ? c; code while(1){} executed from flash all peripherals disabled: cclk = 12 mhz - 4.6 - ma cclk = 24 mhz - 9 - ma cclk = 33 mhz - 12.2 - ma all peripherals enabled: cclk = 12 mhz - 6.6 - ma cclk = 24 mhz - 10.9 - ma cclk = 33 mhz - 14.1 - ma sleep mode; v dd(3v3) = 3.3 v; t amb =25 ?c; all peripherals disabled cclk = 12 mhz - 1.8 - ma cclk = 24 mhz - 3.3 - ma cclk = 33 mhz - 4.4 - ma deep-sleep mode; v dd(3v3) = 3.3 v; t amb =25 ?c -30- ? a deep power-down mode; v dd(3v3) = 3.3 v; t amb =25 ?c - 720 - na normal-drive output pins (standard port pins, reset ) i il low-level input current v i =0v; - - 100 na i ih high-level input current v i =v dd(io) ; - - 100 na i oz off-state output current v o =0v; v o =v dd(io) ; - - 100 na v i input voltage pin configured to provide a digital function [2] [3] [4] 0- v dd(io) v v o output voltage output active 0 - v dd(io) v v ih high-level input voltage 0.7v dd(io) --v
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 20 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller v il low-level input voltage --0.3v dd(io) v v hys hysteresis voltage - 0.4 - v v oh high-level output voltage low mode; i oh = ? 2 ma v dd(io) ? 0.4 --v high mode; i oh = ? 4 ma v dd(io) ? 0.4 --v v ol low-level output voltage low mode; i ol =2 ma - - 0.4 v high mode; i ol = 4 ma 0.4 i oh high-level output current low mode; v oh = v dd(io) ? 0.4 v ? 2--ma high mode; v oh = v dd(io) ? 0.4 v ? 4--ma i ol low-level output current low mode; v ol = 0 . 4 v 2--m a high mode; v ol = 0 . 4 v 4--m a i ohs high-level short-circuit output current v oh =0v [5] -- ? 45 ma i ols low-level short-circuit output current v ol =v dda [5] --5 0m a i pu pull-up current v i =0v ? 50 ? 80 ? 100 ? a high-drive output pins (pio0_ 27, pio0_28, pio0_29, pio0_12) i il low-level input current v i =0v; - - 100 na i ih high-level input current v i =v dd(io) ; - - 100 na i oz off-state output current v o =0v; v o =v dd(io) ; - - 100 na v i input voltage pin configured to provide a digital function [2] [3] [4] 0- v dd(io) v v o output voltage output active 0 - v dd(io) v v ih high-level input voltage 0.7v dd(io) --v v il low-level input voltage - - 0.3v dd(io) -- v hys hysteresis voltage - - v v oh high-level output voltage low mode; i oh = ? 20 ma v dd(io) ? 0.7 --v high mode; i oh = ? 28 ma v dd(io) ? 0.7 --v v ol low-level output voltage low mode; i ol = 12 ma - - 0.4 v high mode; i ol = 18 ma - - 0.4 v table 7. static characteristics ?continued t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 21 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] including voltage on outputs in 3-state mode. [3] v dd(3v3) and v dd(io) supply voltages must be present. [4] 3-state outputs go into 3-state mode when v dd(io) is grounded. [5] allowed as long as the current limit does not exceed the maximum current allowed by the device. [6] to v ss . i oh high-level output current low mode; v oh = v dd(io) ? 0.7 20--ma high mode; v oh = v dd(io) ? 0.7 28--ma i ol low-level output current v ol =0.4v low mode 12--ma high mode 18 - - ma i ols low-level short-circuit output current v ol =v dd [5] -- m a i pu pull-up current v i =0v ? 50 ? 80 ? 100 ? a i 2 c-bus pins (pio0_10 and pio0_11) v ih high-level input voltage 0.7v dd(io) --v v il low-level input voltage --0.3v dd(io) v v hys hysteresis voltage - 0.05v dd(io) -v v ol low-level output voltage i ols =20 ma - - 0.4 v i li input leakage current v i =v dd(io) [6] -24 ? a v i =5v - 10 22 ? a c i capacitance for each i/o pin on pins pio0_10 and pio0_11 --8pf oscillator pins v i(xtal) crystal input voltage see section 12.1 01 . 81 . 9 5v v o(xtal) crystal output voltage 0 1.8 1.95 v table 7. static characteristics ?continued t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 22 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 10.1 peripheral power consumption the supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the sysahbclkcfg and pdruncfg (for analog blocks) registers. all other blocks are disabled in both registers and no code is executed. me asured on a typical sample at t amb =25 ? c and v dd(3v3) = 3.3 v. 10.2 power consumption power measurements in active, sleep, and deep-sleep modes were performed under the following conditions (see lpc122x user manual ): ? active mode: all gpio pins set to input with external pull-up resistors. ? sleep and deep-sleep modes: all gpio pins set to output driving low. ? deep power-down mode: all gpio pins set to input with external pull-up resistors. table 8. peripheral power consumption peripheral typical current consumption i dd in ma frequency independent 24 mhz 12 mhz system oscillator + pll irc + pll system oscillator irc irc 0.29 - - - - pll (pll output frequency = 24 mhz) 1.87 - - - - wdosc (wdosc output frequency = 500 khz) 0.25 - - - - bod 0.06 - - - - analog comparator 0/1 - 0.05 0.05 0.03 0.02 adc - 1.86 1.85 1.61 1.61 crc engine - 0.04 0.04 0.02 0.02 16-bit timer 0 (ct16b 0) - 0.09 0.09 0.04 0.04 16-bit timer 1 (ct16b 1) - 0.09 0.09 0.04 0.04 32-bit timer 0 (ct32b 0) - 0.08 0.08 0.04 0.04 32-bit timer 1 (ct32b 1) - 0.08 0.08 0.04 0.04 gpio0 - 0.34 0.34 0.17 0.17 gpio1 - 0.34 0.34 0.17 0.17 gpio2 - 0.36 0.37 0.18 0.18 i2c - 0.09 0.09 0.05 0.05 iocon - 0.09 0.10 0.05 0.05 rtc - 0.10 0.10 0.05 0.05 ssp - 0.30 0.29 0.15 0.15 uart0 - 0.52 0.51 0.26 0.26 uart1 - 0.52 0.51 0.26 0.26 dma - 0.18 0.18 0.09 0.09 wwdt - 0.06 0.06 0.03 0.03
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 23 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller conditions: t amb = 25 ? c; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl register; all peripheral clocks disabled; internal pull-up resistors dis abled; bod disabled. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. (3) system oscillator enabled; irc and system pll disabled. fig 5. active mode: typical supply current i dd versus supply voltage v dd(3v3) for different system clock frequencie s (all peripher als disabled) conditions: v dd(3v3) = 3.3 v; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl register; all peripheral clocks disabled; internal pull-up resistors dis abled; bod disabled. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. (3) system oscillator enabled; irc and system pll disabled. fig 6. active mode: typical supply current i dd versus temperature for different system clock frequencies (peripherals disabled) v dd(3v3) (v) 3 3.6 3.4 3.2 002aag186 8 4 12 16 i dd (ma) 0 33 mhz (2) 24 mhz (2) 12 mhz (1) 4 mhz (3) 1 mhz (3) 12 mhz (1) 4 mhz (3) 1 mhz (3) 33 mhz (2) 24 mhz (2) 002aag023 temperature (c) -40 85 35 10 60 -15 4 12 8 16 i dd (ma) 0
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 24 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller conditions: t amb = 25 ? c; active mode entered executing code while(1){} from flash; all peripherals enabled in the sysahbclkctrl register. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. (3) system oscillator enabled with external clock input; irc and system pll disabled. fig 7. active mode: typical supply current i dd versus supply voltage v dd(3v3) for different system clock frequenc ies (all peripherals enabled) conditions: v dd(3v3) = 3.3 v; active mode entered executing code while(1){} from flash; all peripherals enabled in the sysahbclkctrl register. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. (3) system oscillator enabled with external clock input; irc and system pll disabled. fig 8. active mode: typical supply current i dd versus temperature for different system clock frequencies (peripherals enabled) v dd(3v3) (v) 3 3.6 3.4 3.2 002aag187 8 4 12 16 i dd (ma) 0 33 mhz (2) 24 mhz (2) 12 mhz (1) 4 mhz (3) 1 mhz (3) 12 mhz (1) 4 mhz (3) 1 mhz (3) 33 mhz (2) 24 mhz (2) 002aag024 temperature (c) -40 85 35 10 60 -15 4 12 8 16 i dd (ma) 0
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 25 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller conditions: v dd(3v3) = 3.3 v; sleep mode entered from flash; all peripherals disabled in the sysahbclkctrl register (sysahbclk ctrl = 0x1f); all peripheral clocks disabled; internal pull-up resistors dis abled; bod disabled. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. (3) system oscillator enabled with external clock input; irc and system pll disabled. fig 9. sleep mode: typical supply current i dd versus supply voltage v dd(3v3) for different system clock frequencies conditions: bod disabled; all oscillators and analog blocks disabled in the pdsleepcfg register fig 10. deep-sleep mode: typical supply current i dd versus temperature for different supply voltages v dd(3v3) v dd(3v3) (v) 3.0 3.6 3.4 3.2 002aag188 2 3 1 4 5 i dd (ma) 0 33 mhz (2) 24 mhz (2) 12 mhz (1) 1 mhz (3) 4 mhz (3) 002aag190 20 40 30 50 i dd (a) 10 temperature (c) -40 85 35 10 60 -15 v dd(3v3) = 3.6 v 3.3 v 3.0 v
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 26 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 10.3 electrical pi n characteristics fig 11. deep power-down mode: typical supply current i dd versus temperature for different supply voltages v dd(3v3) 002aag189 0.7 0.9 0.8 1.0 i dd (a) 0.6 temperature (c) -40 85 35 10 60 -15 v dd(3v3) = 3.6 v 3.3 v 3.0 v conditions: v dd(io) = 3.3 v fig 12. high-drive pins: typical high-level output voltage v oh versus high-level output current i oh i oh (ma) 0 48 32 16 002aag175 2.8 2.4 3.2 3.6 v oh (v) 2 low mode -40 c +25 c +70 c +85 c low mode -40 c +25 c +70 c +85 c
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 27 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller conditions: v dd(io) = 3.3 v fig 13. high-drive pins: typical low-level output voltage v ol versus low-level output current i ol conditions: v dd(io) = 3.3 v. fig 14. i 2 c-bus pins (high current sink): typical low-level output voltage v ol versus low-level output current i ol i ol (ma) 0 48 32 16 002aag310 0.4 0.8 1.2 v ol (v) 0 low mode -40 c +25 c +70 c +85 c high mode -40 c +25 c +70 c +85 c i ol (ma) 0 48 36 24 12 002aag180 0.4 0.2 0.6 0.8 v ol (v) 0 -40 c +25 c +70 c +85 c
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 28 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller conditions: v dd(io) = 3.3 v. fig 15. normal-drive pins: typical low-level output voltage v ol versus low-level output current i ol conditions: v dd(io) = 3.3 v. fig 16. normal-drive pins: typical high-level output voltage v oh versus high-level output source current i oh 002aag181 i ol (ma) 0 16 12 8 4 0.4 0.8 1.2 v ol (v) 0 - 40 c +25 c +70 c +85 c - 40 c +25 c +70 c +85 c low mode high mode i oh (ma) 0 16 12 8 4 002aag182 2.6 2.2 3.0 3.4 v oh (v) 1.8 -40 c +25 c +70 c +85 c -40 c +25 c +70 c +85 c low mode high mode
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 29 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller conditions: v dd(io) = 3.3 v. fig 17. typical pull-up current i pu versus input voltage v i v i (ma) 0 3 2 1 002aag185 -60 -40 -80 -20 0 i pu (ma) -100 +85 c +70 c +25 c -40 c
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 30 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 10.4 adc characteristics [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] conditions: v ss =0v, v dd(3v3) =3.3v. [3] the adc is monotonic, there are no missing codes. [4] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 18 . [5] the integral non-linearity (e l(adj) ) is the peak difference between the c enter of the steps of the actual and the ideal transfer curve after appropriate adj ustment of gain and offset errors. see figure 18 . [6] the offset error (e o ) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. see figure 18 . [7] the gain error (e g ) is the relative difference in percent betw een the straight line fitting the actual transfer curve after removing offset error, and the strai ght line which fits the ideal transfer curve. see figure 18 . [8] the absolute error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 18 . [9] t amb = 25 ? c; maximum sampling frequency f s = 257 khz and analog input capacitance c ia = 1 pf. [10] input resistance r i depends on the sampling frequency fs: r i = 1 / (f s ? c ia ). table 9. adc static characteristics t amb = ? 40 ? c to +85 ? c unless otherwise specified; adc frequency 9 mhz, v dd(3v3) = 3.0 v to 3.6 v. symbol parameter conditions min typ [1] max unit v ia analog input voltage 0 - v dd(3v3) v c ia analog input capacitance - - 1 pf e d differential linearity error [2] [3] [4] -- ? 1lsb e l(adj) integral non-linearity [2] [5] -- ? 2.5 lsb e o offset error [2] [6] -- ? 1lsb e g gain error [2] [7] -- ? 3lsb e t absolute error [2] [8] -- ? 3lsb f c(adc) adc conversion frequency - - 257 khz r i input resistance [9] [10] -- 3.9 m ?
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 31 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 18. adc characteristics 002aae787 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dd(3v3) ? v ss 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 32 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 10.5 bod static characteristics [1] interrupt levels are selected by writing the level value to the bod control register bodctrl, see lpc122x user manual . table 10. bod static characteristics [1] t amb =25 ? c. symbol parameter conditions min typ max unit v th threshold voltage interrupt level 1 assertion - 2.25 - v de-assertion - 2.39 - v interrupt level 2 assertion - 2.54 - v de-assertion - 2.67 - v interrupt level 3 assertion - 2.83 - v de-assertion - 2.93 - v reset level 1 assertion - 2.04 - v de-assertion - 2.18 - v reset level 2 assertion - 2.34 - v de-assertion - 2.47 - v reset level 3 assertion - 2.62 - v de-assertion - 2.76 - v
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 33 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 11. dynamic characteristics 11.1 power-up ramp conditions [1] see figure 19 . [2] the wait time specifies the time the power supply must be at levels below 400 mv before ramping up. table 11. power-up characteristics t amb = ? 40 ? c to +85 ?c. symbol parameter conditions min typ max unit t r rise time at t = t 1 : 0 < v i ?? 400 mv [1] 0- 500 ms t wait wait time [1] [2] 12 - - ? s v i input voltage at t = t 1 on pin v dd 0 - 400 mv condition: 0 < v i ?? 400 mv at start of power-up (t = t 1 ) fig 19. power-up ramp v dd 0 400 mv t r t wait t = t 1 002aag001
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 34 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 11.2 flash memory [1] erase and programming times are valid over the lifetime of the device (minimum 20000 cycles). [2] number of program/erase cycles. 11.3 external clock [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. table 12. dynamic characte ristics: flash memory t amb = ? 40 ? c to +85 ? c; v dd(3v3) over specified ranges. symbol parameter conditions min max unit t er erase time for one page (512 byte) [1] -2 0ms for one sector (4 kb) [1] 162 ms for all sectors; mass erase [1] -2 0ms t prog programming time one word (4 bytes) [1] -4 9 ? s four sequential words [1] -1 94 ? s 128 bytes (one row of 32 words) [1] -7 65 ? s n endu endurance [2] 20000 - cycles t ret retention time 10 - years table 13. dynamic characte ristics: external clock t amb = ? 40 ? c to +85 ? c; v dd(3v3) over specified ranges. [1] symbol parameter conditions min typ [2] max unit f osc oscillator frequency 1 - 25 mhz t cy(clk) clock cycle time 40 - 1000 ns t chcx clock high time t cy(clk) ? 0.4--ns t clcx clock low time t cy(clk) ? 0.4--ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns fig 20. external clock timing (with an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 35 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 11.4 internal oscillators [1] parameters are valid over operating te mperature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at nom inal supply voltages. [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] the typical frequency spread over processing and temperature (t amb = ?40 ? c to +85 ? c) is ? 40 %. [3] see the lpc122x user manual . table 14. dynamic characterist ics: internal oscillators t amb = ? 40 ? c to +85 ? c; v dd(3v3) over specified ranges. [1] symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency - 11.88 12 12.12 mhz fig 21. internal rc oscillator frequency versus temperature table 15. dynamic characterist ics: watchdog oscillator symbol parameter conditions min typ [1] max unit f osc(int) internal oscillator frequency divsel = 0x1f, freqsel = 0x1 in the wdtoscctrl register; [2] [3] -7.8 - khz divsel = 0x00, freqsel = 0xf in the wdtoscctrl register [2] [3] - 1700 - khz 002aag020 11.95 12.05 12.15 f osc(rc) (mhz) 11.85 temperature ( c) ?40 85 35 10 60 ?15 vdd = 3.6 v 3.3 v 3.0 v 12 mhz + 1% 12 mhz ? 1%
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 36 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 11.5 i 2 c-bus [1] parameters are valid over operating tem perature range unless otherwise specified. [2] a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. [3] c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall times are allowed. [4] the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection re sistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [5] in fast-mode plus, fall time is specified the same for bot h output stage and bus timing. if se ries resistors are used, desig ners should allow for this when c onsidering bus timing. [6] thd;dat is the data hold time that is measured from the fa lling edge of scl; applies to data in transmission and the acknowl edge. [7] the maximum t hd;dat could be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time. this maximum must only be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [8] tsu;dat is the data set-up time that is measured with respec t to the rising edge of scl; applies to data in transmission and the acknowledge. [9] a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system but the requirement t su;dat = 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stre tch the low period of the scl signal, it must output the next data bit to the sda line t r(max) + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. al so the acknowledge timing must meet this set-up time. table 16. dynamic characteristics: i 2 c-bus pins t amb = ? 40 ? c to +85 ? c. [1] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz fast-mode plus 0 1 mhz t f fall time [2] [3] [4] [5] of both sda and scl signals standard-mo de - 300 ns fast-mode 20 + 0.1 ? c b 300 ns fast-mode plus - 120 ns t low low period of the scl clock standard-mode 4.7 - ? s fast-mode 1.3 - ? s fast-mode plus 0.5 - ? s t high high period of the scl clock standard-mode 4.0 - ? s fast-mode 0.6 - ? s fast-mode plus 0.26 - ? s t hd;dat data hold time [6] [2] [7] standard-mode 0 - ? s fast-mode 0 - ? s fast-mode plus 0 - ? s t su;dat data set-up time [8] [9] standard-mode 250 - ns fast-mode 100 - ns fast-mode plus 50 - ns
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 37 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller fig 22. i 2 c-bus pins clock timing 002aaf425 t f 70 % 30 % sda t f 70 % 30 % s 70 % 30 % 70 % 30 % t hd;dat scl 1 / f scl 70 % 30 % 70 % 30 % t vd;dat t high t low t su;dat
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 38 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 12. application information 12.1 xtal input the input voltage to the on-chip oscillators is limited to 1.8 v. if the oscillator is driven by a clock in slave mode, it is recommended that th e input be coupled through a capacitor with c i = 100 pf. to limit the input voltage to the specified range, choose an additional capacitor to ground c g which attenuates the input voltage by a factor c i /(c i + c g ). in slave mode, a minimum of 200 mv(rms) is needed. 12.2 xtal printed circuit boar d (pcb) layout guidelines the crystal should be connected on the pcb as close as poss ible to the oscillator input and output pins of the chip. take care that the load capacitors c x1 ,c x2 , and c x3 in case of third overtone crystal usage have a common ground plane. the external components must also be connected to the ground plain. loops must be made as small as possible in order to keep the noise coupled in via the pcb as small as possible. also parasitics should stay as small as possible. values of c x1 and c x2 should be chosen smaller accordingly to the increase in parasitics of the pcb layout. fig 23. slave mode operation of the on-chip oscillator lpc1xxx xtalin c i 100 pf c g 002aae788
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 39 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 12.3 electromagnetic co mpatibility (emc) radiated emission measurements according to the iec61967-2 standard using the tem-cell method are shown for the lpc1227fbd64/301 in ta b l e 1 7 . [1] iec levels refer to appendix d in the iec61967-2 specification . table 17. electromagnetic compatibility (e mc) for part lpc1227fbd64/301 (tem-cell method) v dd = 3.3 v; t amb = 25 ? c. parameter frequency band system clock = unit 12 mhz 24 mhz 33 mhz input clock: irc (12 mhz) maximum peak level 150 khz - 30 mhz ? 4.2 ? 3.8 ? 6.4 db ? v 30 mhz - 150 mhz 7.3 5.4 9 db ? v 150 mhz - 1 ghz 16.4 20.1 23.4 db ? v iec level [1] - mll- input clock: crystal oscillator (12 mhz) maximum peak level 150 khz - 30 mhz ? 4.8 ? 4 ? 6.6 db ? v 30 mhz - 150 mhz 6.9 5.6 10 db ? v 150 mhz - 1 ghz 16.3 20.3 22.3 db ? v iec level [1] - mll-
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 40 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 13. package outline fig 24. package outline lqfp100 unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o o 0.08 0.08 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot407-1 136e20 ms-026 00-02-01 03-02-20 d (1) (1)(1) 14.1 13.9 h d 16.25 15.75 e z 1.15 0.85 d b p e e a 1 a l p detail x l (a ) 3 b 25 c d h b p e h a 2 v m b d z d a z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 5 10 mm scale lqfp100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm sot407-1
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 41 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 14. soldering fig 25. reflow soldering of the lqfp100 package sot407-1 dimensions in mm occupied area footprint information for reflow soldering of lqfp100 package ax bx gx gy hy hx ayby p1 p2 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy p1 p2 c sot407-1 solder land c generic footprint pattern refer to the package outline drawing for actual layout 17.300 17.300 14.300 14.300 0.500 0.560 0.280 1.500 0.400 14.500 14.500 17.550 17.550
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 42 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 15. references [1] lpc122x data sheet , http://www.nxp.com /microcontrollers [2] pcf8576d data sheet , http://www.nxp.com /microcontrollers
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 43 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 16. revision history table 18. revision history document id release date data sheet status change notice supersedes lpc12d27 v.1 20110920 product data sheet - -
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 44 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 17.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 17.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? 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stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
lpc12d27 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 20 september 2011 45 of 46 nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 17.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors lpc12d27 32-bit arm cortex-m0 microcontroller ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 20 september 2011 document identifier: lpc12d27 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 7 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 functional description . . . . . . . . . . . . . . . . . . 14 7.1 lpc1227 microcontroller . . . . . . . . . . . . . . . . 14 7.2 lcd driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2.1 general description . . . . . . . . . . . . . . . . . . . . 14 7.2.2 functional description. . . . . . . . . . . . . . . . . . . 15 7.2.3 reset state of the lcd controller and pins . . . 15 7.2.4 lcd bias generator . . . . . . . . . . . . . . . . . . . . 15 7.2.5 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2.5.1 internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2.6 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.2.7 display register . . . . . . . . . . . . . . . . . . . . . . . . 16 7.2.8 segment outputs. . . . . . . . . . . . . . . . . . . . . . . 16 7.2.9 backplane outputs . . . . . . . . . . . . . . . . . . . . . 16 7.2.10 display ram . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17 9 thermal characteristics . . . . . . . . . . . . . . . . . 18 9.1 thermal characteristics. . . . . . . . . . . . . . . . . . 18 10 static characteristics. . . . . . . . . . . . . . . . . . . . 19 10.1 peripheral power consumpt ion . . . . . . . . . . . . 22 10.2 power consumption . . . . . . . . . . . . . . . . . . . . 22 10.3 electrical pin characteristics . . . . . . . . . . . . . . 26 10.4 adc characteristics . . . . . . . . . . . . . . . . . . . . 30 10.5 bod static characteristics. . . . . . . . . . . . . . . . 32 11 dynamic characteristics . . . . . . . . . . . . . . . . . 33 11.1 power-up ramp conditions . . . . . . . . . . . . . . . 33 11.2 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . 34 11.3 external clock . . . . . . . . . . . . . . . . . . . . . . . . . 34 11.4 internal oscillators. . . . . . . . . . . . . . . . . . . . . . 35 11.5 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 12 application information. . . . . . . . . . . . . . . . . . 38 12.1 xtal input . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12.2 xtal printed circu it board (pcb) layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12.3 electromagnetic compatibility (emc) . . . . . . . 39 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 40 14 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 15 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 16 revision history . . . . . . . . . . . . . . . . . . . . . . . 43 17 legal information . . . . . . . . . . . . . . . . . . . . . . 44 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 44 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 44 17.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 45 18 contact information . . . . . . . . . . . . . . . . . . . . 45 19 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

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